CPU

openhwgroup

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

rsd-devel

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

oneapi-src

oneAPI-samples

Samples for Intel® oneAPI Toolkits

rust-embedded

riscv

Low level access to RISC-V processors

splinedrive

kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

Wren6991

Hazard3

3-stage RV32IMACZb* processor with debug

chipsalliance

Cores-VeeR-EH1

VeeR EH1 core

lvyufeng

step_into_mips

一步一步写MIPS CPU

rejunity

z80-open-silicon

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

antonblanchard

microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

sergeykhbr

riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

cvut

qtrvsim

RISC-V CPU simulator for education purposes

openhwgroup

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

trivialmips

nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

openrisc

mor1kx

mor1kx - an OpenRISC 1000 processor IP core

pulp-platform

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

PrincetonUniversity

openpiton

The OpenPiton Platform