HDL

ghdl

ghdl

VHDL 2008/93/87 simulator

The-OpenROAD-Project

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

hdl-util

hdmi

Send video/audio over HDMI on an FPGA

open-sdr

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

google

xls

XLS: Accelerated HW Synthesis

WangXuan95

FPGA-FOC

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

LeiWang1999

FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

FPGAwars

apio

:seedling: Open source ecosystem for open FPGA boards

TerosTechnology

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

openhwgroup

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

ben-marshall

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

QShen3

CNN-FPGA

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

SI-RISCV

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

olofk

serv

SERV - The SErial RISC-V CPU

ultraembedded

riscv

RISC-V CPU Core (RV32IM)

drom

awesome-hdl

Hardware Description Languages

kartik-v

bootstrap-star-rating

A simple yet powerful JQuery star rating plugin with fractional rating support.

firesim

firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

ultraembedded

cores

Various HDL (Verilog) IP Cores

projf

projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

zachjs

sv2v

SystemVerilog to Verilog conversion

The-OpenROAD-Project

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

OpenTimer

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

m-labs

nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen