mortbopet
Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
OPEN PROJECT DIRECTORY
53 projects
mortbopet
A graphical processor simulator and assembly editor for the RISC-V ISA
cyring
CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.
simdutf
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers, Ghostty and Bun.
openhwgroup
Functional verification project for the CORE-V family of RISC-V cores.
mnurzia
32-bit RISC-V CPU in ~800 lines of C89
MoonbaseOtago
VRoom! RISC-V CPU
Wren6991
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
platformio
Your Gateway to Embedded Software Development Excellence :alien:
SI-RISCV
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
risc0
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
kfrlib
Fast, modern C++ DSP framework, FFT, Sample Rate Conversion, FIR/IIR/Biquad Filters (SSE, AVX, AVX-512, ARM NEON, RISC-V RVV)
olofk
SERV - The SErial RISC-V CPU
ultraembedded
RISC-V CPU Core (RV32IM)
:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.
firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
OpenXiangShan
Open-source high-performance RISC-V processor
YosysHQ
PicoRV32 - A Size-Optimized RISC-V CPU
chipsalliance
Rocket Chip Generator
BrunoLevy
Learning FPGA, yosys, nextpnr, and RISC-V
SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
openhwgroup
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
probe-rs
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
renode
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
darklife
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!