Xilinx
Vitis-Tutorials
Vitis In-Depth Tutorials
OPEN PROJECT DIRECTORY
96 projects
Xilinx
Vitis In-Depth Tutorials
ZipCPU
A small, light weight, RISC CPU soft core
aolofsson
Verilog library for ASIC and FPGA designers
cariboulabs
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
ultraembedded
32-bit Superscalar RISC-V CPU
EttusResearch
The USRP™ Hardware Driver Repository
verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
YosysHQ
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
oneapi-src
Samples for Intel® oneAPI Toolkits
circuitvalley
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
splinedrive
RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34
Xilinx
Dataflow compiler for QNN inference on FPGAs
Silverr12
Detailed Instructions on the creation of custom/modified DMA (attack) Firmware based on pcileech-fpga
chipsalliance
VeeR EH1 core
fpgasystems
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
dhm2013724
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
WangXuan95
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器,可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备,只需要3个FPGA普通IO,而不需要额外的接口芯片。
alexforencich
Verilog AXI stream components for FPGA implementation
KastnerRG
Parallel Programming for FPGAs -- An open-source high-level synthesis book
open-sdr
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
nickg
VHDL compiler and simulator
Obijuan
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
WangXuan95
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
emsec
HAL – The Hardware Analyzer