RISC-V

riscv-boom

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

rcore-os

rCore-Tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

lowRISC

ibex

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

riscv-mcu

e203_hbirdv2

The Ultra-Low Power RISC-V Core

sipeed

MaixPy-v1

MicroPython for K210 RISC-V, let's play with edge AI easier

o8vm

octox

Unix-like OS in Rust inspired by xv6-riscv

TheThirdOne

rars

RARS -- RISC-V Assembler and Runtime Simulator

liangkangnan

tinyriscv

A very simple and easy to understand RISC-V core.

hughperkins

VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

chipsalliance

riscv-dv

Random instruction generator for RISC-V processor verification

rustsbi

rustsbi

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see prototyper folder.

ultraembedded

biriscv

32-bit Superscalar RISC-V CPU

LekKit

RVVM

The RISC-V Virtual Machine

openhwgroup

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

rsd-devel

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

rust-embedded

riscv

Low level access to RISC-V processors

libriscv

libriscv

The fastest RVA23 RISC-V sandbox

splinedrive

kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

Wren6991

Hazard3

3-stage RV32IMACZb* processor with debug

github0null

eide

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

syntacore

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

chipsalliance

Cores-VeeR-EH1

VeeR EH1 core

sergeykhbr

riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

cvut

qtrvsim

RISC-V CPU simulator for education purposes