Open AI Hardware

beekeeb

piantor

The Piantor Keyboard is a beginner-friendly, easy-to-solder, 42-key or 36-key, diodeless, low profile aggressive column staggered, hotswappable and non-hotswappable, programmable ergonomic mechanical split keyboard powered by Raspberry Pi Pico or other compatible RP2040 boards. It is based on the Cantor Keyboard.

WangXuan95

Xilinx-FPGA-PCIe-XDMA-Tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

eldraco

Salamandra

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

emsec

hal

HAL – The Hardware Analyzer

tjhorner

upsy-desky

Make your standing desk smarter

PyHDI

Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

rejunity

z80-open-silicon

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

chipsalliance

firrtl

Flexible Intermediate Representation for RTL

JulianKemmerer

PipelineC

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

konosubakonoakua

FPGA_MCU_Debugger_Collections

各种LInk大合集

alexforencich

verilog-i2c

Verilog I2C interface for FPGA implementation

antonblanchard

microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

sergeykhbr

riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Xilinx

XRT

Run Time for AIE and FPGA based platforms

icebreaker-fpga

icebreaker

Small and low cost FPGA educational and development board

cardonabits

haxo-hw

Haxophone, an electronic musical instrument that resembles a saxophone

KitSprout

AltiumDesigner_PcbLibrary

AD 元件庫，AltiumDesigner PCB Library

fguzman82

gateGPT

Full Transformer into a custom chip. microGPT in RTL, generating names on a Virtex-5 FPGA at ~56k tokens/second.

dtysky

FPGA-Imaging-Library

An open source library for image processing on FPGA.

cvut

qtrvsim

RISC-V CPU simulator for education purposes

ultraembedded

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

seldridge

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

ucb-bar

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

openhwgroup

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.