ASIC/芯片

CDFER

JLCPCB-Kicad-Library

A set of symbols, footprints and 3d models of the basic components from JLCPCB's smt assembly

luke-jr

bfgminer

Modular ASIC/FPGA miner written in C, featuring overclocking, monitoring, fan speed control and remote interface capabilities.

olofk

serv

SERV - The SErial RISC-V CPU

ultraembedded

riscv

RISC-V CPU Core (RV32IM)

ultraembedded

cores

Various HDL (Verilog) IP Cores

OpenTimer

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

librelane

librelane

ASIC implementation flow infrastructure, successor to OpenLane

google

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

openhwgroup

cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

pConst

basic_verilog

Must-have verilog systemverilog modules

The-OpenROAD-Project

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

pulp-platform

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

ucb-bar

gemmini

Berkeley's Spatial Array Generator

aolofsson

oh

Verilog library for ASIC and FPGA designers

hughperkins

VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

ultraembedded

biriscv

32-bit Superscalar RISC-V CPU

splinedrive

kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

chipsalliance

Cores-VeeR-EH1

VeeR EH1 core

rejunity

z80-open-silicon

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

seldridge

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

openhwgroup

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

ichi4096

vivado-on-silicon-mac

Installs Vivado on M1/M2/M3 macs

VLSI-EDA

PoC

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

pulp-platform

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core