RISC-V

mortbopet

Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

cyring

CoreFreq

CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.

simdutf

simdutf

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers, Ghostty and Bun.

openhwgroup

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

mnurzia

rv

32-bit RISC-V CPU in ~800 lines of C89

MoonbaseOtago

vroom

VRoom! RISC-V CPU

Wren6991

RISCBoy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

platformio

platformio-core

Your Gateway to Embedded Software Development Excellence :alien:

SI-RISCV

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

risc0

risc0

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

kfrlib

kfr

Fast, modern C++ DSP framework, FFT, Sample Rate Conversion, FIR/IIR/Biquad Filters (SSE, AVX, AVX-512, ARM NEON, RISC-V RVV)

olofk

serv

SERV - The SErial RISC-V CPU

ultraembedded

riscv

RISC-V CPU Core (RV32IM)

iDoka

awesome-embedded-software

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.

firesim

firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

YosysHQ

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

chipsalliance

rocket-chip

Rocket Chip Generator

BrunoLevy

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

SpinalHDL

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

openhwgroup

cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

probe-rs

probe-rs

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

renode

renode

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

darklife

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!