SoC

enjoy-digital

litex

Build your hardware, easily!

fbdesignpro

sweetviz

Visualize and compare datasets, target values and associations, with one line of code.

lnis-uofu

OpenFPGA

An Open-source FPGA IP Generator

SpinalHDL

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

langhuihui

monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

The-OpenROAD-Project

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

riscv-mcu

e203_hbirdv2

The Ultra-Low Power RISC-V Core

splinedrive

kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

chipsalliance

Cores-VeeR-EH1

VeeR EH1 core

sergeykhbr

riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

openhwgroup

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

trivialmips

nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.