ZipCPU
wb2axip
Bus bridges and other odds and ends
开放项目目录
96 个项目
ZipCPU
Bus bridges and other odds and ends
m-labs
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
samitbasu
A framework for writing FPGA firmware using the Rust Programming Language
logisim-evolution
Digital logic design tool and simulator
BrunoLevy
Learning FPGA, yosys, nextpnr, and RISC-V
SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
openhwgroup
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
alexforencich
Verilog Ethernet components for FPGA implementation
darklife
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
corundum
Open source FPGA-based NIC and platform for in-network compute
jbush001
GPGPU microprocessor architecture
GlasgowEmbedded
Scots Army Knife for electronics
alexforencich
Verilog AXI components for FPGA implementation
amaranth-lang
A modern hardware definition language and toolchain based on Python
SpinalHDL
Scala based HDL
pConst
Must-have verilog systemverilog modules
analogdevicesinc
HDL libraries and projects
FPGAwars
:snowflake: Visual editor for open FPGA boards
riscv-mcu
The Ultra-Low Power RISC-V Core
ufrisk
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
YosysHQ
nextpnr portable FPGA place and route tool
trabucayre
Universal utility for programming FPGA
pulp-platform
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
aws
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit