chipsalliance
firrtl
Flexible Intermediate Representation for RTL
OPEN PROJECT DIRECTORY
94 projects
chipsalliance
Flexible Intermediate Representation for RTL
JulianKemmerer
PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
alexforencich
Verilog I2C interface for FPGA implementation
antonblanchard
A tiny Open POWER ISA softcore written in VHDL 2008
sergeykhbr
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
fguzman82
Full Transformer into a custom chip. microGPT in RTL, generating names on a Virtex-5 FPGA at ~56k tokens/second.
ultraembedded
A DDR3 memory controller in Verilog for various FPGAs
seldridge
Repository for basic (and not so basic) Verilog blocks with high re-use potential
ucb-bar
Simple RISC-V 3-stage Pipeline in Chisel
WangXuan95
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
trivialmips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
VLSI-EDA
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
openrisc
mor1kx - an OpenRISC 1000 processor IP core
jofrfu
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
zephray
A Pi emulating a GameBoy sounds cheap. What about an FPGA?
jks-prv
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS (archived)
vicharak-in
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
VHDL-LS
A fast VHDL language server and analysis library written in Rust
clash-lang
Haskell to VHDL/Verilog/SystemVerilog compiler
PrincetonUniversity
The OpenPiton Platform
xiaop1
HDLBits website practices & solutions
olofk
An abstraction library for interfacing EDA tools