HDL

dalance

svls

SystemVerilog language server

samitbasu

rust-hdl

A framework for writing FPGA firmware using the Rust Programming Language

logisim-evolution

logisim-evolution

Digital logic design tool and simulator

OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

chipsalliance

chisel

Chisel: A Modern Hardware Design Language

verilator

verilator

Verilator open-source SystemVerilog simulator and lint system

chipsalliance

rocket-chip

Rocket Chip Generator

SpinalHDL

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

openhwgroup

cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

alexforencich

verilog-ethernet

Verilog Ethernet components for FPGA implementation

darklife

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cocotb

cocotb

cocotb: Python-based chip (RTL) verification

layoutBox

PinLayout

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

langhuihui

monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

riscv-boom

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

jbush001

NyuziProcessor

GPGPU microprocessor architecture

alexforencich

verilog-axi

Verilog AXI components for FPGA implementation

amaranth-lang

amaranth

A modern hardware definition language and toolchain based on Python

SpinalHDL

SpinalHDL

Scala based HDL

pConst

basic_verilog

Must-have verilog systemverilog modules

analogdevicesinc

hdl

HDL libraries and projects

chipsalliance

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

FPGAwars

icestudio

:snowflake: Visual editor for open FPGA boards

The-OpenROAD-Project

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.